The invention relates to electrically erasable programmable read only memory devices, specifically those devices having buried bit line array structure, sometimes referred to as ACE or ACEE (advanced contactless EPROM or EEPROM). The invention contemplates such arrays having word erase capability.
Buried bit line EPROM or EEPROM arrays are known which utilize buried, doped lines, usually n+ conductivity doped crystalline silicon under thick field oxide regions as bit lines for the array. The doped lines then act as the source/drain regions of the transistors of the memory cells. A typical EPROM of the advanced contactless array type is disclosed, for example in U.S. Pat. No. 4,698,900, issued Oct. 13, 1987 to A. Esquivel and assigned to Texas Instruments Incorporated.
EEPROMs (electrically erasable programmable read only memories) have been developed which both erase and program information from a single memory cell by tunneling charges through insulators. Such devices are discussed in "Comparisons and Trends in Today's Dominant E.sup.2 Technologies", by S. Lai, et al., 1986 IEDM Digest of Technical Papers, pp. 580-583.
Hybrids of the EEPROMs discussed above are also known, such as Flash EEPROMs which program by either avalanche injection or tunneling and which erase by tunneling. Such devices have generally been limited to bulk erasure in which the whole memory array is erased electrically at once. An example of a Flash EEPROM which is programmed by avalanche injection and erased by tunneling is described by F. Matsuoka, et al., "A 256K Flash EEPROM Using Triple Level Polysilicon Technology", 1985 ISSCC Digest of Technical Papers, pp. 168-169.